产生伪的VHDL语言程序

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成-Communications base-band signal generator design, the use of single-chip input frequency and waveform, in the FPGA to achieve the frequency and waveform generation

vga很好的学习材料，测试程序，欢迎下载(vga good learning materials, testing procedures, please download)

说明：  Xilinx原语的使用介绍，特别全面，希望对大家有所帮助，(Introduction to the use of Xilinx primitives, particularly comprehensive,I hope it will be helpful to you all.)

comparator code for micarowind

The VHDL Cookbook First Edition July, 1990 Peter J. Ashenden Dept. Computer Science University of Adelaide South Australia

说明：  FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)

关于两种实现pwm的方法 基于51单片机设计-on two methods to achieve PWM 51 microcontroller-based design

USB+FPGA电路设计原理图，实际的电路板运行正常，很有参考意义。-usb_sch

Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic