通过VHDL语言的例子，对FPGA的VHDL语言的原型（第六章）是

DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.(DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.)

circuit design with VHDL e-book MIT Press....

采用Verilog HDL设计,在掌宇智能开发板上得到实现 根据抢答器的原理，整个电路可划分为三部分：采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the entire electric circuit may divide is three parts: The sampling electric circuit, the gate control the electric circuit and the decoding circuit

eda技术与vhdl课件,很经典的学习课件-VHDL EDA technology and courseware, it is a classic learning courseware

说明：  RLC Test程序,一个电子竞赛的题目。里面有详尽的源代码。(RLC Test procedures, an electronic race issue. There are detailed source code.)

台湾产数字编码电位器EC11的使用测试程序(Taiwan-digital encoder potentiometer EC11 of testing procedures)

3-8译码器地简单实现，采用QUARTUSii5.0环境编译-3-8 decoder to realize a simple, using the compiler QUARTUSii5.0 environment

CycloneIV控制采样芯片AD9248-20MHz，VHDL语言(CycloneIV control sampling chip AD9248-20MHz, VHDL language)

programming of and gate

用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.