通过VHDL语言的例子，对FPGA的VHDL语言的原型（第六章）是

设计了一个电子时钟，功能包括定点报时，设置闹钟，校时等(Designed an electronic clock, features include fixed-point timekeeping, setting alarms, school hours, etc.)

The aim of the ECG simulator is to produce the typical ECG waveforms of different leads and as many arrhythmias as possible. My ECG simulator is a matlab based simulator and is able to produce normal lead II ECG waveform.

zedboard的资料说明书，可以帮助你理解(zedboard data sheets, can help you understand)

如何编写测试文件，，test bench的编写方法和是列，，总结的非常好的东西(how to code test bench in verilog)

用VHDL语言写的VGA核心,是个很好很齐全的核心,有很多功能.-write VHDL VGA core, is a very good subset of the core, has a lot of functions.

Learning Verilog Chinese Version Part 8

液晶显示屏显示汉字“年”的驱动程序VHDL(nian VHDL)

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

4X4 KEYPAD 的密码比较模块，可以核对6位的密码-4x4 KEYPAD password comparison module, can check the password 6

这个文档回答了很多关于AHB总线在使用上经常遇到的问题(this doc gives a lot of answers for using AHB bus when doing design)