异步FIFO的实现可以全面、可核查的]关键词：…

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SDIO slave, written in verilog, does not support SPI mode.

关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL

6对于进入密码锁的按键，假设复位后七个灯显示" 0"，使用sw1、sw2 2，然后只要按下并松开sw2，七个灯上就显示" 2"，而只要按下并松开sw1，七个灯上就正确显示值" 1

基于FPGA的误码测试仪 （已注释） --锁相环-M序列生成模块--数据接口模块- --模拟信道模块---本地M序列生成模块--同步模块--误码统计模块--显示模块-(FPGA-based BER tester)

You well get all details about project and microcontroller

本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。 (In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.)

用zynq实现片内的数模转换，基于最新的zynq平台(zynq xadc on FPGA arm)

spi driver: Analog Device DAC ad9788 SPI Controller

基于avgt开发板的jesd204b源代码，需要安装Quartus软件(Avgt development board based on the jesd204b source code)