本源码详细介绍了UART的经典实例，敬请下载，谢谢适用

一篇关于多相滤波器的论文,讲解了关于多信道的实现与仿真。(A paper about the polyphase filter，explained about the realization of multi-channel and simulation )

HDL example source code 3/5 jkff_a

xilinx公司的FPGA实现数字视频信号处理器。语言是VHDL。-Xilinx FPGA to achieve the company

状态机的性能考察.rar 状态机的性能考察.rar-Study the performance of state machine. Rar inspect the performance of state machine. Rar

说明：  一个编码解码系统，其中包含一个信号发生器（用查找表方式实现）、一个m序列生成器（用来编码和解码用）、一个FiFo队列用来做缓存以及用串口方式进行收发读取数据。(An encoding and decoding system, which includes a signal generator (implemented by look-up table), an m-sequence generator (used for encoding and decoding), a FIFO queue for caching, and a serial port for receiving, transmitting and reading data.)

这是一个VHDL项目，用于在VIRTEX-4 xc4vsx35 FPGA板中执行接收信号的14位ADC。

利用verilog写的PWM 程序，来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)

fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)

un controller pi par le langage VHDL xilinx ise design 13.2

Quartus_II_9.0破解器有明确的破解Quartus_II_9.0的步骤(Quartus_II_9. 0 cracked the clear cracked Quartus_II_9. 0 steps)