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This is what I found online vhdl language used to write the sdram controller cod...
这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱:wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
- 2022-03-26 03:30:04下载
- 积分:1
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median
说明: 用verilog编辑的中值滤波器!语言旁表有注释方便理解!(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)
- 2008-11-03 09:21:18下载
- 积分:1
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Avgt_jesd204b_ad9250_ed
基于avgt开发板的jesd204b源代码,需要安装Quartus软件(Avgt development board based on the jesd204b source code)
- 2020-11-26 14:29:32下载
- 积分:1
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234
在接收信号的数字化、软化的实现中,数字下变频起着重要的作用。本文首先介绍了数字下
变频的组成结构,然后详细分析了数字下变频的工作原理,描述了在实现数字下变频时,设计方案所
采用的高效滤波器———CIC 滤波器和多相抽取滤波器的结构和原理。最后,用通过Simulink 对数字
下变频的性能进行了仿真。在仿真的基础上使用Insight 公司的FPGA 开发系统,用测试电路实测了
数字下变频的性(In the receiving digital signal, softening the realization, the digital down-conversion plays an important role. This article first introduced the digital down conversion of the composition, and then a detailed analysis of digital down conversion of the working principle described in the realization of digital down conversion, the design used in high-performance filters--- CIC filters and multi-phase extraction filter structure and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of)
- 2021-03-16 21:29:21下载
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verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用....
verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
- 2022-08-24 07:12:53下载
- 积分:1
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UART receiver and transmitter using vhdl
这是执行高速的代码通用异步收发器代码是用VHDL写的语言.UART是一种在传输端进行并行输入和串行输出,在接收端进行串行输入和并行输出的算法。
- 2022-02-06 12:51:51下载
- 积分:1
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shift_regeister
用blockram实现移位寄存器,开发语言为verilog hdl(Shift register with blockram achieve the development language for the verilog hdl)
- 2020-08-13 22:18:29下载
- 积分:1
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xapp1161
多相滤波系统的设计与实现,有MATLAB仿真程序,有sysgen的系统仿真,还有VHDL代码,其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on
)
- 2021-02-15 17:29:47下载
- 积分:1
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verilog支持noise噪声的端口port
verilog支持noise噪声的端口port, 可以用于仿真运行.
评估噪声影响
Verilog port that supports noise and can be used for simulation run.
Evaluate noise effects
- 2022-07-25 10:35:21下载
- 积分:1
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抢答器仿真
本文件包括整个基于QuartusII实现的抢答器模块,其下包括各个分模块,实现效果较不错。
- 2022-08-10 14:21:30下载
- 积分:1