VHDL_ 两个电路计数上 / 下液晶显示语言 VHDL (海 mạch đếm lên/xuống hiển 施耐液晶 bằng ngôn ngữ VHDL)

通信系统帧同步信号的设计与实现，巴克码识别器系统完整VHDL程序，本人课程设计，完全能正常运行，程序运行环境为Quartus II 7.2 (32-Bit)，win7系统。编译码模块、分频模块、门限设置模块、仿真电路和程序都有。相互交流，共同学习！！

最终FFT 64点使用定点。

FPGA课件，个人感觉不错，希望对大家有帮助(FPGA software, personal feel good, I hope all of you help)

讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been

verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。(verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.)

该PPT是一个内部教学资料，想学习EDA技术的朋友可以看看这个教学资料。-The PPT is an internal teaching materials, want to learn EDA technologies friends can look at the teaching and learning materials.

在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)

说明：  关于quartus与modelsim 仿真(about quartus and modelsim simulator)

HDLC通信协议，FPGA实现，包含源文件和仿真测试文件。(HDLC comunication)