最后64点FFT

这是一个用结构化语言编写的25抽头LMS算法建模.VHDL加法器/减法器、乘法器、延迟元件的代码分别编写并用LMS代码实例化。

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)-Electronic Design Competition works _ audio signal source analyzer FPGA (first prize)

FIFO的verilog描述(Verilog description of the FIFO)

采用高速AD的存储示波器设计，基于EP1C3板GWADDA板存储示波器，内有说明文件-AD using high-speed storage oscilloscope design, based on EP1C3 board GWADDA board storage oscilloscope, which has the documentation

一篇关于FIFO设计以及FPGA设计的文章-FIFO 1 on the design and FPGA design article

电子设计自动化中的计数器的实现程序，基于VHDL语言完成的-Electronic design automation in the realization of counter procedures, based on the VHDL language completed

An Alarm Project Writen in VHDL for FPGA Devices

说明：  实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)

这个我也太清楚是什么 反正师兄们说有用 发大家-I am also very clear that what is useful anyway, say senior U.S. fa

Alter kit FPGA de2-35 This project shows a cascade motion through board leds.-Alter kit FPGA de2-35 This project shows a cascade motion through board leds.