康塔德7 0 - 9999 en显示segmentos verilog

此部分verilog代码为ldpc的最小和译码算法verilog源代码。verilog源代码适用于Xilinx和altera开发环境。

小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)

实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)

saber的仿真模型，是一个电源的，经过调试已经成功(The simulation model of the saber, is a power, after commissioning has been successfully)

学习verilog中常见的编程方法和例子。欢迎大家下载、试用。谢谢大家的支持！

基于 FPGA的 VGA 接口的实例，在这里，我们先要考虑 vga_interface.v 支持的图像分辨率，亦即 16x 16 。所以 RAM 所需要的储存空间是 16Bits x 16Words。RAM 和 FIFO 一样，要访问 RAM 的时候都需 要拉高 xx_En_Sig 信号。由于RAM 包含 16Bits 所以 Write_Data 和 Read_Data, 皆 是16 位的位宽。当然，16Words 表示了 xx_Addr_Sig 是 4位的位宽。

verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)

说明：  介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining the signal integrity becomes increasingly more difficult. For many of todays commonly used video interfaces, there are devices that can be used to assist in this matter. However, the use of such a device is only partially documented in the DisplayPort specification for the receiving image device, which means that the receiving side of the video link is free to choose its own implementation. This report presents, together with background research and design decisions, a suggestion for such an implementation. This implementation would need to be compatible towards a wide range of possible video Source devices and DisplayPort cables.)

16位右移位寄存器 下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)

uart通信的Verilog实现,包含rx tx 以及testbench(Verilog implemention of UART telecommunicate)