7×7交叉使用Verilog

LTE is an abbreviation for Long Term Evolution.

EDK tutorial 1 ----------------

an 16 bit ripple carry adder

该代码实现了俄罗斯方块旋转，左右移动，快速下降，计分和VGA显示等基本功能(This code realizes the basic functions of Russian square rotation, left-right movement, rapid decline, scoring and VGA display.)

FPGA 帧同步源代码 调试无错误 ALTERA 平台(Frame synchronization FPGA)

可以产生8比特的采样波形，非常不错的VHDL程序(Sampling can produce 8-bit waveform, very good VHDL program)

说明：  实现AXI,AXI-Lite乒乓地址的传输，AXI,AXI-Lite已经封装成内核，可直接修改后使用(Realize the transmission of table tennis address of Axi and Axi Lite. Axi and Axi Lite have been encapsulated into a kernel, which can be directly modified and used)

使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。(The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..)

这是一个学习verilog HDL的好资料，适合于初学者，讲解详细，从浅入深，学好这个语言，是学习硬件描述语言的好东西，好资料！

sobel边缘检测，用于图像处理。实现了该算法在FPGA上的实现代码。(Sobel edge detection for image processing.Implementation of the algorithm to achieve the FPGA code.)