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spi_dac_ad7394_ad7395.v
Verilog code of SPI configurator for DAC AD7394 and AD7395
- 2014-09-11 21:58:15下载
- 积分:1
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sp605_BRD_rdf0033_13.2_c
spartan605评估板测试代码。xilinx官方资料(spartan605 uation board test code)
- 2014-12-23 22:27:45下载
- 积分:1
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4jieshuzilboqi
四阶数字滤波器 用不同的算法设计数字滤波器,并且有详细的是用方法(Fourth-order digital filter design with a different digital filter algorithms and a detailed method is)
- 2011-04-25 18:18:16下载
- 积分:1
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dingshi
定时器加数码管显示源码,以及test bench测试模块源码,经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分:1
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四位数码管1~9999加法计数
verilog HDL语言程序,运行后实验板四位数码管依次加法计数,从1到9999计数,超过后即溢出,重新从1开始
计数
- 2022-02-07 01:27:29下载
- 积分:1
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FPGA 64位除法器 verilog
用verilog语言实现的除法器,实现方式为移位减
- 2023-09-02 08:35:03下载
- 积分:1
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APB_timer
说明: 设计一个挂载在 APB 总线上的计数器,按照 APB 的时序给计数器赋值,主
机通过地址对计数器进行配置,通过数据输入端口给计数器设置计数器最大值,
并通过数据输出端口输出计数器的计数值。该设计还设置了一个计数完成信号,
当计数器满足模式配置后的计数要求时,会将该信号拉高(A counter mounted on the APB bus is designed. The counter is assigned according to the sequence of APB
The computer configures the counter through the address and sets the maximum value of the counter through the data input port,
And output the count value of the counter through the data output port. The design also sets a count completion signal,
When the counter meets the counting requirements after the mode configuration, the signal will be pulled high)
- 2021-05-14 17:30:02下载
- 积分:1
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tsobbellh
这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件,可在QuartusII或MaxplisII下综合与与仿真,并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测,同时还能实现其它的图像模块化处理算法,例如高斯滤波,平滑等。
(This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.)
- 2012-08-23 22:17:19下载
- 积分:1
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Poiseuille_BB_solution
LBM用于Poiseuille流初学者程序,直接反弹格式(LBM Poiseuille)
- 2021-02-24 15:49:39下载
- 积分:1
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pdf
说明: 一种基于FPGA的调频连续波方位向多通道
FMCW SAR的实时成像信号处理方法及FPGA,包
括:步骤一、计算重构矩阵;步骤二、重构方位向
多通道数据,包括:步骤2 .1、对各个通道的回波
数据沿方位向分别间隔补零,并进行方位向傅里
叶变换;步骤2 .2、将方位向傅里叶变换之后各个
通道方位向相同位置的点组合为一个向量并与
重构矩阵相乘,得到重构完成的方位向数据;(An azimuth multichannel FMCW based on FPGA
FMCW SAR real-time imaging signal processing method and FPGA, package
Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation
Multichannel data, including: step 2.1, echo of each channel
The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out
Step 2.2, after the azimuth Fourier transform
The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data
Step 2.3. Repeat step 2.3 for the data of different distance gates)
- 2020-02-07 19:47:41下载
- 积分:1