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Verilog数控分频器的设计

于 2022-11-07 发布 文件大小:17.91 kB
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分析参考代码中的各语句功能、设计原理、逻辑功能,根据图1的波形提示,编写相应的Testbench文件代码,并用Modelsim进行仿真(仿真可以跳过时钟分频到100hz进程)。 在此基础上进行硬件验证。实验方法为:将clk接20Mhz时钟信号,rst_n接核心板开关S1,fout接发光二极管SD0,预置值d从DKA0-DKA7输入,改变d的输入,从发光二极管SD0判断输出信号的频率。

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