classics_verilog_codes_for_commom_projects

verilog 写的工程，是个基于流水线的乘法器(verilog write the works, is based on a pipelined multiplier)

关于一个串行数据输入 根据时序将数据分两路输出的程序 (on a serial data input timing will be based on output data using two procedures)

说明：  802.16d 的卷积编码和解码的VHDL实现(802.16d cc encoding and decoding,writing in VHDL)

D触发器是最简单，最常用，最具代表性的时序元件，它是现代数字系统设计中最基本的底层时序单元，甚至是ASIC设计的标准单元。JK和T触发器都由D触发器构建而来。D触发器的描述包含了Verilog对时序电路的最基本和典型的表达方式，同时也包含了Verilog许多最具特色的语言现象。

Anticipated Adder for Xilinx

四位拨妞开关作为输入，当输入值变化时将其转化成两位输出(The four DIP Niu switch as an input, when the input value changes, be converted into two output)

实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)

对于已获得的脉冲包络采样序列，需测量的脉冲特征参数主要有：脉冲幅值(PA)、脉冲到达时间(TOA)和脉冲宽度(PW)。实际测量中，脉冲波形的形状是各种各样的，但其主要的参数有脉冲幅度、脉冲宽度、脉冲周期、脉冲占空比、脉冲前沿(上升时间)、脉冲后沿(下降时间)、脉冲上冲、脉冲下冲、脉冲下垂、脉冲顶部不平度等，脉冲参数的计量主要就是对这些参数进行计量。本程序包实现基于FPGA实现脉冲宽度和重复周期的测量。(Who have access to the pulse envelope sample sequence, the pulse measurement to be the main characteristic parameters are: pulse amplitude (PA), pulse time of arrival (TOA) and pulse width (PW). The actual measurement, the pulse shape is a wide variety of shapes, but its main parameters of the pulse amplitude, pulse width, pulse period, pulse duty cycle, pulse leading edge (rise time), pulse along (down time), the red pulse, pulse undershoot, pulse droop, pulse irregularities, such as at the top, the measurement of pulse parameters is mainly the measurement of these parameters. The package FPGA-based pulse width and repetition to achieve the measurement cycle.)

这个源代码是EasyFPGA030的例程。欢迎大家下载、试用。谢谢大家的支持！

FPGA编写的三角波发生器，可以产生100HZ～500KHZ以上的三角波，波形稳定(FPGA prepared triangular wave generator, can produce more than 100HZ ~ 500KHZ triangle wave, waveform stability)