Verilog languages with four arithmetic logic unit ALU, functional reference to 7...

实现SIGMA-DELTA Modulator的veriolog代码(sigma-delta moudulator for RFPLL )

台湾IC中心VHDL讲义，内容详细，适合IC前端设计参考(Taiwan s IC Center VHDL handouts, detailed reference design for front-end IC)

带自适应波特率发生器UART实现，经过FPGA验证的！-UART baud rate generator with adaptive realization, after FPGA validation!

使用VHDL进行分频器设计，主要是一些分频的东西，整数分频，小数分频，奇次分频和偶次分频-Divider using VHDL to design, mainly because some sub-band stuff, integer divider, fractional-N, odd and even sub-sub-sub-sub-band frequency

关于VHDL编程的教程,比较系统的讲解,很有用的书-a book about VHDL

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped

说明：  生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)

说明：  以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)

以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn