Verilog languages with four arithmetic logic unit ALU, functional reference to 7...

JOP字节码获取的源码，很重要，具体FPGA中实现-JOP byte code access to the source code is important to achieve specific FPGA

说明：  led学习控制l44444444444444(led verilog led ccccccc)

to learn bout development of vhdl code

基于DS1302芯片的VERILOG 语言数字钟。可实现年月日时分秒显示。(DS1302 chip-based language VERILOG digital clock. Date can be achieved when every minute display.)

从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)

实现dds功能，利用quartus软件， 子模块包括加法器，锁相环，date-rom 利用原图将各模块综合，利用ps2键盘控制频率及相位。-Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated, using ps2 keyboard to control the frequency and phase.

说明：  2018全国大学生FPGA创新设计大赛南京总决赛封闭测试题目，以及自己编写的verilog和testbench，欢迎学习借鉴(The closed test topic of the 2018 National Undergraduate FPGA innovation design competition Nanjing finals, as well as Verilog and testbench compiled by ourselves, are welcome to learn)

用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用-use of the VHDL standard ARM processor core source code procedures, the reuse

说明：  阿尔泰PCI8664的采集卡labview程序(PCI8664，labview，programm)

用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!