文章论述如何将向modelsim中添加仿真库，包括添加xilinx,altera,actel公司的仿真库的方法...

verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)

《FPGA数字信号处理与工程应用实践附光盘》配套源代码(FPGA DSP and their applications with verilog HDL)

计数器是数字系统中使用最多的时序电路，它不仅能用于对时钟脉冲计数，还可以用于分频、定时、产生节拍脉冲和脉冲序列以及进行数字运算等。(Counter is the most frequently used sequential circuit in digital system. It can be used not only for counting clock pulses, but also for frequency division, timing, generating beat pulses and pulse sequences, and performing digital operations.)

频率计介绍了用VHDL语言编写的频率计的程序，详细编写了如何测频，如何计数频率。-Cymometer introduce VHDL language with the frequency of the procedure in detail how to prepare a frequency measurement, how to count the frequency.

说明：  4位二进制加法计数器的两种不同VHDL的描述,与比较。(4-bit binary addition of two different counter VHDL description, and more.)

一个异步FIFO的verilog实现论文-err

用verilog HDL语言编写的fifo存储器源文件 (Using Verilog language HDL FIFO memory source file)

uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device

在 VHDL 中实现的游戏 实施LFSR创建与随机游戏板 随机颜色。使用VGA控制器和块内存 我们显示游戏板，并写入它取决于某些规则。用户 可以控制如何密游戏板填充，则显示什么颜色， 而如何快速模拟。

光栅尺的四细分和辩向电路，并具有计数器功能，利用Quartus综合，可以参考-Grating four segments and the dialectic to the circuit, and have counter functions, using Quartus integrated, can refer to