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router_routing
片上网络NOC基于fpga实现的,routing模块。(NOC-chip networks realized fpga-based, routing module.)
- 2021-03-03 17:19:32下载
- 积分:1
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GIF图像查看器的VHDL代码
vhdl code for GIF Image Viewer
- 2023-05-09 12:40:03下载
- 积分:1
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sim_uart
uart 收发器 verilog 代码,实现自收发功能
sys clk = 25m, baud 9600 停止位1, 无校验位;
代码实现了串口自收发功能,及把从 PC 收到的内容都发送会 PC, 其他波特率,自行修改代码即可,在 alter 的FPGA 上调试通过;
(verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )
- 2010-10-10 21:49:46下载
- 积分:1
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Spartan6_GTP_PCIe_xfest_2009_v1_0
采用Xilinx公司的Spartan6 FPGA设计PCI Express的详细参考资料(Xilinx' s PCI Express, Spartan6 FPGA design, detailed reference information)
- 2012-08-30 10:01:33下载
- 积分:1
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alarm
闹钟设计,VHDL,源代码。闹钟设计,VHDL,源代码。(Alarm clock design, VHDL, the source code.)
- 2011-05-23 18:30:29下载
- 积分:1
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业界标准的Verilog语法格式
verilog标准语法,还有很多的样例参考,学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)
- 2020-06-15 22:50:02下载
- 积分:1
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alu
the 8 bit alu by verilog
- 2011-05-26 11:25:43下载
- 积分:1
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Xilinx的FPGA开发DEMO例程,功能相对来说比较全面,适合新手参考。...
Xilinx的FPGA开发DEMO例程,功能相对来说比较全面,适合新手参考。-Xilinx FPGA development DEMO routines, function relatively comprehensive reference suitable for novice.
- 2022-02-21 21:55:12下载
- 积分:1
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synplify-hand-book(English)
Syplify经典英文教程。内含众多实验例程,Lab 1 Basic Synplify Run;Lab 2 Analyzing Critical Path and Assigning Timing;Lab 3 FSM (Finite State Machine) Compiler Constraints and Attributes(Syplify classic English tutorial. Contains numerous experiments routine, you can help learners to quickly grasp Syplify tips, is a rare foreign experiments tutorial.)
- 2015-04-20 09:01:06下载
- 积分:1
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用verilog实现了一个数字秒表的设计
用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
- 2022-08-03 10:15:12下载
- 积分:1