基于VHDL的rsc（7,5）递归卷积编码器

很多VHDL例子，没有测试，供大家参考-VHDL many examples, there is no test, for your reference

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

n_bit_paralleLoadShiftRegJK

i2c硬件程序,字节读、字节写，在modelsim6.0通过编译-the soft for i2c

此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP

基于VHDL的SDH专用芯片的TOP-DOWN设计， 内有全套源码以及图片，内容详尽，绝对真实可靠！(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)

在FPGA开发板显示字符串,采用VHDL语言,以简单的功能说明FPGA的开发流程.-In the FPGA development board shows the string, using VHDL language, in a simple functional description FPGA-development process.

VHDL code for 32 byte RAM

用Verilog实现1602的配置及功能。正确编译与实现(Realized by Verilog 1602 configurations and functions. Compilation and implementation of the right)

一个很好的利用verilog编程实现的cpu程序，一定要好好利用。-a good use of the Verilog Programming cpu procedures, we must make good use of.