The use of Altera' s FPGA

梁祝音乐verilog code --适用于QUATUS II 开发环境下，适合于verilog入门学员(the verilog code of liangzhu )

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

一个关于跨越异步时钟边界传输数据的解决方案(The solution of transfering data across asynchronous clock boundary.)

课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL

VHDL 与数字电路设计程序参考书所有程序 1-VHDL and digital circuit design process all the procedures a reference book

fpga实现的IIC通信的例程，注释很详细(fpga implementation of serial communication routines, comments in great detail)

FPGA的经典例程，可以进行移植和借鉴使用(FPGA' s classic routines, can be transplanted and learn to use)

VHDL语言实现H.264的opencore，内涵说明文档、源码和文献等资料。 -VHDL language H.264 realize the opencore, meaning that documents, information such as source code and documentation.

本练习的目的是检查加法、减法和乘法运算电路。每个

QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)