数字电子设备上下计数器的实现

16*16点阵横向移动显示！采用QUARTUS II 9.0编译通过！(16* 16 dot matrix display lateral movement! Compiled by using QUARTUS II 9.0!)

说明：  基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

saber的仿真模型，是一个电源的，经过调试已经成功(The simulation model of the saber, is a power, after commissioning has been successfully)

fsk在matlab上的仿真实现，一段简单的代码小程序(fsk on matlab simulation in the implementation of a simple small program code)

本文描述了fpga中的亚稳态时如何产生的，以及如何计算亚稳态的平均无故障时间。对了解亚稳态有帮助。-This paper describes the sub-fpga how the steady state, as well as how to calculate the metastable MTBF. The understanding of metastable helpful.

FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告(FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language)

坦克游戏用VHDL语言编写。Altera的随身携带套件DE1。PS2键盘接口和VGA

nrf24l01发送代码，verilog实现NRF24L01通信(NRF24L01 send code, Verilog to achieve NRF24L01 communication)

Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.