数字电子设备上下计数器的实现

说明：  该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。(This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像形态学部分,腐蚀,膨胀,细化算法(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image morphology section, corrosion, swelling, thinning algorithm)

根据按键控制状态机状态转换，内含仿真波形文件

用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company"s paid Multiplier ip core.

使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)

FPGA做机器人舵机控制系统，verilog(FPGA to do the robot servo control system, verilog)

利用verilog语言实现了SHA-1机密算法，具体算法与加密芯片ds28e01一致。(Using Verilog to achieve the SHA-1 secret algorithm, the specific algorithm is consistent with the encryption chip ds28e01.)

基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.(Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the button to switch the modulation of 25 , 50 , 75 and short press button to switch the modulation signal frequency 1k, 1.5k, 2k, 2.5k.)

VHDL 洗衣机程序，可实现定时、报警、洗衣，脱水等等功能。底层为VHDL文件，顶层为电路图连接

基于CPLD芯片EPM570的verilog hdl串口程序(the UART verilog hdl code based on CPLD chip-- EPM570)