verilog编写的计算百分比模块

现色彩空间转换R’G’B’ to Y’CbCr的VHDL源代码。-Kabuki现rough cleaning转Connaught distance RGB to Y CbCr cavity VHDL Daitou Tungsten measurements 。

FPGA驱动TCD1304AP线阵CCD，并经采集将数据通过串口传输至上位机(FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial)

利用FPGA设计游戏设计，真人版超级玛丽，VGA显示(Using FPGA design game design, live-action version of Super Mario, VGA display)

由于在网上很难下载到EDA技术－窦衡的PPT，所以本人经过学习后做成word，供大家下载。只针对VHDL语言部分和所有的程序。-Because the Internet is difficult to download to EDA technology- Douheng of the PPT, so I made after learning after the word, for all to download. Only for part of the VHDL language and all the procedures.

是用VHDL语言写的对A/D转换模块的控制程序，希望对大家有帮助。-VHDL language is used on the A/D conversion module control procedures, in the hope that everyone has to help.

直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.

说明：  用verilog HDL编程实现的基于DAC0832的三角波信号，可借鉴编程实现DAC0832芯片控制(Programming with verilog HDL DAC0832-based triangular wave signal, we may learn programming DAC0832 chip control)

基于DE2开发板的VGA显示模块，仅供大家参考(DE2 development board based on the VGA display module, for your reference)

卷积程序的Verilog程序，实现卷积功能(Convolution program Verilog program to achieve convolution function)

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第三个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The third document