FPGA simulation examples, Verilog coding, the process in detail, code easy to un...

60进制减法 相比较 代码效率高 可以进行级联-60 compared to 229 subtraction efficient code can be concatenated

说明：  一篇关于LDPC解码算法的FPGA用VHDL实现的PDF文件，老外写的，还可以，可以参考，欢迎大家下载！(A PDF about the FPGA implementation of LDPC algorithm, written by foreigners, but also, you can refer to, welcome to download!)

I2C slave 代码，可以完成从机功能-about I2C slave code about I2C slave code

Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface

PLL中的TDC和DCO代码,是TI公司团队的，相当经典的代码，非常不错(the code of TDC and DCO)

A Full adder using half adder unit in vhdl

This programa execute calc of CRC by use a table.

基于单片机的DDS数字信号发生器设计，可以产生正弦波。三角波等(Design of DDS digital signal generator based on MCU, can produce sine wave. Triangular wave)

fpga正弦波发生函数，可用于自动生成rom文件(fpga sine wave generating function)

该模块采用cordic算法计算正弦和余弦，并采用参数化方式实现。 ；包中存在其他模块。