本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!-16 CUPIP nuclear, full of good things to run, can be directly used to use!

很好的fft学习程序感兴趣的同学可以看哈，下载一下。(it is very good )

说明：  运用Verilog 语言进行数字积分法，将X轴和Y轴进行插补运算。(Verilog language using digital integration method, the X axis and Y axis interpolation operations.)

quartus 17.1 安装包，我现在用的就是(Quartus 17.1 installation kit, what I am using now is)

program send sms by sim900 module

驱动0.96寸的oled显示数字和字母，(Drive 0.96 inch OLED to display numbers and letters.)

早迟门（early late gate），比特同步算法，该文档详细的说明了早迟门算法的原理以及具体的实现步骤(Early late gate (early late gate), bit synchronization algorithm, the document explains in detail the principles of early-late gate method and the specific implementation steps)

基于fpga和xinlinx ise的串行通信vhdl程序，希望对你有所帮助！-xinlinx and ideally serial communications VHDL process, and I hope to help you!

DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.

protel经典教程，并附有一张电路设计原理图(protel classic tutorials, together with a circuit design schematic)