FPGA simulation examples, Verilog coding, the process in detail, code easy to un...

六十进制计数器，VHDL编写的计数器，本科电子的可能有些实验可以用到(counter Possible experiments of undergraduate electronics can be used)

异步fifo实现，通过双口ram实现异步fifo(Asynchronous FIFO implementation, through dual port RAM to achieve asynchronous FIFO)

VHDL开发环境，电梯控制系统，实现电梯的上下传送控制。-VHDL development environment, elevator control system, transmission control up and down elevators.

跑马灯 简单实用很适合初学者 希望对大家有用-Marquee is simple and practical very suitable for beginners want to be useful to everyone

axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)

说明：  包含一个ALU，实现斐波那契数列的计算。1.接受两个6位二进制输入。2.通过手动输入的时钟驱动每个周期进行一次计算。3.结果输出到led灯（使用NEXYS4开发板）(Including an ALU to realize the calculation of Fibonacci sequence. 1. Accept two 6-bit binary inputs. 2. Each cycle is driven by a clock input manually. 3. Output to LED lamp (using NEXYS4 development board))

程序主要用硬件描述语言（VHDL）实现： 单片机与FPGA接口通信的问题-procedures major hardware description language (VHDL) to achieve : MCU and FPGA interface communication problems

这是基于Nios II的12864液晶点亮程序，包含汉字、字符等(This is a program which is based on Nios II ,its function is light the 12864 LCD that including Chinese characters, characters)

shift register. vhdl verilog

sdh帧同步，实现sdh帧搜索，预同步，同步，保护等各态的功能(SDH frame synchronization SDH frame search, pre-sync, synchronization, protection, the function of each state)