FPGA simulation examples, Verilog coding, the process in detail, code easy to un...

Altera board Mp3 project

it performs the serail dividing operations

verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."

Alter kit FPGA de2-35 This project shows a cascade motion through board leds.-Alter kit FPGA de2-35 This project shows a cascade motion through board leds.

de2,altera fpga

BISS-B 源代码。包含传感器模式和寄存器模式(BISS-B source code. Includes sensor mode and register mode)

VHDL fft 源程序，直接运行就可以，很好的一个程序-VHDL fft source code can be run directly, a very good program

tlm基本框架，生产消费模型例子 tlm基本框架，生产消费模型例子 tlm基本框架，生产消费模型例子(tlm basic framework, examples of production and consumption model)

生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)