-
A VHDL design with the use of powerful 32
一个使用VHDL设计的具有强大功能的32位CPU,这个文件包含了与之配套的PCI位码文件及配置程序。-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of the PCI code files and configuration procedures.
- 2022-08-10 06:36:50下载
- 积分:1
-
一篇用VHDL实现快速傅立叶变换的论文
一篇用VHDL实现快速傅立叶变换的论文,包括原理分析和代码实现,印度圣雄甘地大学M.A.学院提供(VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat)
- 2004-10-05 11:06:01下载
- 积分:1
-
M_SSB_100
由乘法器组成 单边带信号产生的 仿真源代码 msm (Composed of single sideband signal by the multiplier generated simulation source code msm)
- 2007-07-25 14:59:29下载
- 积分:1
-
This is a JPEG codec the VHDL code
这是一个JPEG的编解码的VHDL程序代码-This is a JPEG codec the VHDL code
- 2023-05-21 08:00:03下载
- 积分:1
-
fpga驱动单个灯构成的点阵的程序
程序设置了fpga 的 5x5点阵驱动程序,代码相对比较简洁,这个程序可以作为fpga输出控制,驱动稳压芯片工作,进而点灯
- 2022-05-18 13:42:56下载
- 积分:1
-
基于fpga的出租车计费系统,采用自顶向下的设计方法
基于fpga的出租车计费系统,采用自顶向下的设计方法-FPGA-based billing system of a taxi, using top-down design methodology
- 2022-07-21 01:07:13下载
- 积分:1
-
华为经典FPGA设计全套入门技巧
说明: 华为FPGA设计全套资料,学习FPGA的朋友可以下载看看。(Huawei FPGA design a full set of materials, friends learning FPGA can download and see.)
- 2019-04-02 13:54:48下载
- 积分:1
-
SASX
Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC
- 2020-06-24 11:40:02下载
- 积分:1
-
baseband_verilog
verilog实现的基带信号编码,整个系统分为六个模块,分别为:时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)
- 2009-10-08 10:19:34下载
- 积分:1
-
VGA
verilog vga 图像处理(verilog vga)
- 2013-10-15 19:00:16下载
- 积分:1