用VHDL编写的JK触发器

方案组成模块及系统框图 本方案设计主要由以下模块组成 1：顶层模块 2：数据输入排序模块 3：系统控制模块 4：RAM控制器模块 5：ROM控制器模块 6：蝶型单元模块(Program composition module and system diagram The design of this scheme is mainly composed of the following modules 1: top module 2: data input sorting module 3: system control module 4:RAM controller module 5:ROM controller module 6: butterfly type unit module)

飞思卡尔智能车芯片模块程序 MC9S12XS128 测试通过(freescale smart car for MC9S12XS128)

verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,

用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

用窗函数法设计一个线性相位FIR数字低通滤波器，用理想低通滤波器作为逼近滤波器，通带截止频率为0.2 ，阻带截止频率为0.4 ，阻带衰减不小于-40dB。(Window function method to design a linear phase FIR digital low-pass filter, as an ideal low-pass filter for approximation filter passband cutoff frequency of 0.2 stopband cutoff frequency of 0.4, the stop-band attenuation of less than-40dB.)

fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

this a test keyboard code -this is a test keyboard code

说明：  OFDM信号的发送与接收 ，需要自取。时域图，模糊图，削峰。(Sending and receiving of OFDM signal)

这是OFDM调制matlab的程序，中间详细描述了调制的过程，希望对大家有用。(This is the OFDM modulation matlab procedures, a detailed description of the intermediate modulation process, I hope useful.)