用VHDL编写的JK触发器

AD conversion using LTC1298

此代码实现4人表决功能，4人中有三人同意即为通过。(Four voting)

FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考(FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design)

使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation

交通灯通过数码管显示，几种模式可调，还可以时间可设，适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)

AD706在Sparten6使用的FPGA代码，测试通过(AD706 FPGA Code In Sparten6)

DSP28335与FPGA通过spi通信，此程序为28335为主接收程序(DSP28335 and FPGA through the SPI communication, this procedure for the 28335 receiving procedures)

高速FIFO，verilog设计。速度高达130Mhz(High-speed FIFO, verilog design. Speed up to 130MHz)

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on

网络通信中的MII接口 通常将4位nibble数据送出，此程序将4位数据组合成8位数据并行输出（8比特==1个字节）。。完全可用 同时包含84转换(The MII network interface usually sent four nibble data, this procedure will be 4-bit data into 8-bit parallel output data (8 bits == 1 byte). . Completely available at the same time contains 84 conversion)