本文通过大量的例子讲解VHDL。对于初学者来说是一本非常好的 教材...

内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging

说明：  该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。(This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.)

基于FPGA的运动控制系统设计，包含位置、速度控制等(motion control)

说明：  Verilog实现液晶1602显示,学习使用(Verilog LCD1602)

Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.-Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.

--author: Suntion Tang --date: 2008-6-7 -- two warning --modify: By Suntion Tang at 2008-6-14 --description: 顶层文件，由于此系统简单， -- 且底层文件不多，故放弃原理图描述，采用VHDL语言描述-author: Suntion Tang date: 2008-6-7 two warning modify: By Suntion Tang at 2008-6-14 description: the top-level documents, as a result of this system is simple, and not more than the bottom of a document, they give up the schematic description of the use of VHDL language description

verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)

离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.

802.1as gptp标准包解析verilog模块。用于实现EAVB协议的重要部分。(802.1as gptp verilog module, part of EAVB procotol)

该书介绍了英特尔的80x86CPU和一些串行通信芯片，以及汇编语言。(The book introduces the Intel 80x86CPU and some serial communications chip, and assembly language.)