这是我的毕业设计的SVPWM使永磁交流同步电动机…

在QUARTUS II上实现（7,4）汉明码的译码VHDL语言设计((7,4)Hamming decoder)

本实验实现了一个小的乒乓游戏，VGA显示,代码下载的FPGA板子上验证通过，效果很好。(The experimental realization of a small ping-pong game, VGA display, download the code verified by the FPGA board, with good results.)

代码为ahb interface ，用verilog编写的,包括仿真和综合。(Code for the interface AHB, written in Verilog, including simulation and synthesis.)

jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)

运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)

LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL

四位数字乘法器，在quartus8.0下仿真时序图 -mult4

通过编写verilog语言完成数据的在液晶LCD1602显示(By writing verilog language to complete the data displayed on the LCD LCD1602)

vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)

D触发器的基本功能的理解及应用，特别是记忆传输功能使用WAIT语句编写地理解-D flip-flop understanding of the basic functions and applications, in particular the memory transfer function using the WAIT statement is prepared to understand