-
基于fpga和xinlinx ise的串行通信vhdl程序,希望对你有所帮助!
基于fpga和xinlinx ise的串行通信vhdl程序,希望对你有所帮助!-xinlinx and ideally serial communications VHDL process, and I hope to help you!
- 2023-05-29 05:45:03下载
- 积分:1
-
Verilog 编写的网卡DM9000A的IP核,altera公司寄的DE2系统中的源程序核...
Verilog 编写的网卡DM9000A的IP核,altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
- 2022-02-06 18:05:18下载
- 积分:1
-
WCDMA_DPD
WCDMA数字直放站中数字预失真研究及其FPGA实现(WCDMA Digital Repeater digital pre-distortion and its FPGA implementation)
- 2011-10-16 19:24:50下载
- 积分:1
-
DDS_DAC_Output
本工程使用A7系列FPGA产生DDS,用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)
- 2019-05-06 10:05:10下载
- 积分:1
-
exercise
使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。(Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.)
- 2014-02-20 16:20:33下载
- 积分:1
-
PiSo
8位并行输入的数转换成串行输出,是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)
- 2020-11-30 21:59:27下载
- 积分:1
-
CH372
USB设备接口的驱动程序,采用verilogHDL语言编写,并包含相关说明资料(USB device driver interface, using verilogHDL language, and contains descriptive information)
- 2014-01-03 02:23:08下载
- 积分:1
-
StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分:1
-
图书馆的IEEE
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_ARITH.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
- 2022-03-24 00:58:30下载
- 积分:1
-
《Verilog HDL 程序设计教程》6
《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6
- 2022-02-21 13:38:55下载
- 积分:1