FPGA

基于fpga和xinlinx ise的串行通信vhdl程序，希望对你有所帮助！-xinlinx and ideally serial communications VHDL process, and I hope to help you!

Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear

WCDMA数字直放站中数字预失真研究及其FPGA实现(WCDMA Digital Repeater digital pre-distortion and its FPGA implementation)

本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)

使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。(Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.)

8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)

USB设备接口的驱动程序，采用verilogHDL语言编写，并包含相关说明资料(USB device driver interface, using verilogHDL language, and contains descriptive information)

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL

《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6