基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。...

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

阿尔法贝塔滤波器，是卡曼滤波器的简化，比卡曼滤波器速度快。这是一个实例。(aplha-beta filter is filter that faster than kalman filter)

VHDL servo control from technique of Pulse Width Modulation (PWM )

非常多的verilog实例，对于刚入门者比较有用-lot of verilog example, just beginners more useful

lattice ECP3系列高速FPGA serdes测试代码(lattice ECP3 series high speed serdes test code)

用来检查FPGA通过PHY发送数据时是否有掉帧的现象(FPGA is used to check whether the PHY sends the data out of the frame with the phenomenon of)

verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)

此为EDA设计的分频器模块。可以实现三种不同的频率信号，可以通过使用者自由设置频率大小-This is the design of the divider module EDA. Can achieve three different frequency signals, users can freely set the frequency of the size of

pngenerator的vhdl代码。我们可以在cdma的fpga实现中使用它；

OFDM系统中的相位跟踪模块（Phase_Tracking）的FPGA实现-Phase_Tracking in OFDM sysytems