IIC and xlinx official description of spi interface

verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

xilinx spartan6的pcie pio源代码(xilinx spartan6 pcie pio demo)

hdb3 using language VHDL(Indoor using VHDL language)

说明：  编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法(Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange)

实现了QPSK的调制，使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)

组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)

说明：  设计了六相感应电机的控还原 制平台的硬件结构及其各个组成部分,控制平台结构主要由DSP控制系统和主驱动电路系统以及检测电路系统组成。控制系统采用TI公司的TMS320F2812快速DSP控制芯片。 (This paper designs the hardware structure of the six-phase motor control system and introduces every component. The control platform consists of DSP control system, main drive circuit system and detection circuit system .The control system adopts TMS320F2812 DSP chip of TI Company. 更多还原 )

简要地说明时序约束的内容，对入门级的朋友相当起到引导的作用(Briefly describes the content of timing constraints on entry-level friends rather play a guiding role)

Bucknell Verilog Manual

坦克大战的演示程序 ，实现了基本的人机交互-Battle City demonstration program to achieve the basic human-computer interaction