可综合的Verilog语法和语义，从大学教师cambri…

说明：  VHDL语言的有限状态机法控制8位/12位自动转换通道模数转换器AD7938(VHDL, FSM method to control 8-bit/12-bit ADC AD7938 auto-conversion channel)

it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand

我用的是二进制分频的方法，这种分频方法的分频只能是2n次方，有限制，但是很方便

说明：  写出13个简单的Verilog demon，适合初学者观摩学习。配合实验报告，食用更佳。(Write 13 simple Verilog demon, suitable for beginners to observe and learn. With the experimental report, it is better to eat.)

用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE

中频70M，30M带宽LFM信号，采样率为102.4M，，数字下变频后，还进行了三倍抽取，最后还得到I，Q两路信号 (IF 70M, 30M bandwidth LFM signal, the sampling rate 102.4M, under digital variable frequency after also carried out three times extracted, and finally also received the I and Q signals)

verilog 或门程序 初学者必备。。。。。。。。。。。。(verilog )

Top level Architecture of MIPS Processor

本系统用于GPS中频部分的窄带滤波（AD后的数据经过LMS滤波后去掉窄带干扰，可以抑制20dB以上的干扰）(this system can be imply to anti-narrowband-jamming for GPS IF signal, it can degrade 20dB narrowband jamming)

vhdl code for cyclic cfft control