可综合的Verilog语法和语义，从大学教师cambri…

this project is about FIR FIlter By VHdl codes in the ISE.

该程序用vhdl编写的vga显示的小游戏，到时屏幕上会显示一个小球，一根棒子，一面墙，棒子可以通过按键控制来移动。而小球在不停的运动，遇到墙会反弹。(Game written by the program with VHDL VGA display, the screen will display a small ball, a stick, a wall, stick to move through the key control. Ball in constant motion, encountered the wall will bounce.)

通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made ​ ​ into a single-chip digital clock program)

AD7760模数转换，使能滤波器功能，简单易懂，可进行各种配置 全功能支持，并附加使用说明(AD7760 Full Function Support with Additional Instructions)

说明：  verilog语言编写的简单FPGA 的从机模式 spi 通讯(Slave mode SPI communication of FPGA)

VHDL之二進制轉BCD碼之程式碼，算完整的(Of binary to BCD code VHDL code, operator complete)

四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL

有关verilog的硬件实现VGA设计的代码。-On the Verilog hardware design realize VGA code.

This verilog vga test circuit

Computer Architecture Handbook on Verilog HDL