verilog digital stopwatch to achieve accurate to 10ms

quartus2的中文文档，不是很全，仅供大家学习(quartus2 the Chinese document, not very wide, only for them to learn)

Convolotional Decoding Based on Viterbi Algorithm

这是一本FPGA仿真验证的经典丛书，可以从中学习到如何编写系统的testbench,也可以是IC设计中FPGA原型验证编写系统及testbench的经典书籍。((Kluwer) Writing Testbenches Functional Verification of HDL Models.pdf)

说明：  本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

ac97 VHDL core

说明：  vivado入门使用介绍，初学者入门学习(vivado Instructional pdf)

在图像中

该部分的主要功能是完成基于FPGA的polar码编码。(The main function of this part is to complete the FPGA-based polar code coding.)

采用VHDL编写的一个简单的UART-using VHDL prepared a simple UART

qspi接口控制，指令包括spi、dual spi、quad spi，通过验证，供参考(Qspi interface control, including spi, dual spi, quad spi, for reference.)