DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme

说明：  一维超混沌随机数的生成verilg，还有testbench仿真激励，modelsim的仿真工程。(The generation of one-dimensional hyperchaotic random number verilg, testbench simulation stimulation and Modelsim simulation engineering.)

verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga

使用metlab生产正弦波和三角波的采样值，供vhdl等语言调用来产生波形(use metlab production sine wave and triangular wave of sampling, for languages such as call vhdl to generate waveforms)

USB的vhdl代码，具有很强的指导意义，对FPGA进行usb控制很有帮助！-USB vhdl code, which is of great guiding significance. the FPGA control usb helpful!

从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code

纠错和单故障检测代码使用正交拉丁方是用VHDL语言写的。

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)

用VHDL实现的DDS逻辑，大家可以参考下-DDS achieved using VHDL logic, we can refer to the following

FGAP控制模拟量输出芯片DAC8812(FGAP control analog output chip DAC8812)

vc707 board ucf xdc files