用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。...

本程序为Verlog语言程序，采用QUARTUS6.0编写，程序实现的功能是控制AD2S80的转换和和数据总线上数据的读取-This program is Verlog language program, using QUARTUS6.0 preparation, program implementation function is to control the conversion and AD2S80 and data bus to read data

verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

内置自修复分析仪

在quartus中使用IP核的实际例子与流程-The use of IP in the Quartus practical examples and nuclear flow

能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)

王金明：《Verilog HDL 程序设计教程》程序-Wang Jinming:

FPGA做机器人舵机控制系统，verilog(FPGA to do the robot servo control system, verilog)

altera 公司的15IP源码 亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER

基于FPGA的SOPC嵌入式的流水灯的实现。-Embedded FPGA-based SOPC flow light implementation.

QAM调制，解调matlab代码，包含BPSK，QPSK,16QAM,64QAM,256QAM,1024QAM,4096QAM。其中调制方式。代码通过验证。(QAM modulator,demodulator)