用VHDL语言实现的图像传感器TCD132D的时序驱动代码,时序精准!

基于FPGA的视觉电生理图像刺激系统的设计(Based on the design of FPGA visual electrophysiology image stimulation system)

这通过反馈来实现一个 17 位伪随机的无符号计数器异或的位 0 和 3。 注意 ︰ 如果也绝不是独家使用相反，这会反相平行的位模式 & 这将意味着所有位都零是一种有效模式和所有那些不都是有效。  目前所有的都是有效的。

基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

说明：  VHDL实现的算术逻辑计算单元（ALU），包括modersim测试文件，即仿真结果。(VHDL implementation of the arithmetic logic calculation unit (ALU), including modersim test file, the simulation results.)

TMS320C6678 EVM TMS320C6678 EVM GOOD(TMS320C6678 EVM GOOD TMS320C6678 EVM GOOD)

智能小车用到的c程序，单片机C语言与FPGA的 VHDL语言的结合(Smart car used c program, microcontroller C language and the combination of FPGA VHDL)

基于CPLD芯片EPM570的verilog hdl串口程序(the UART verilog hdl code based on CPLD chip-- EPM570)