用VHDL语言实现的图像传感器TCD132D的时序驱动代码,时序精准!

基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误(IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct)

Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC

libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)

说明：  4位二进制加法计数器的两种不同VHDL的描述,与比较。(4-bit binary addition of two different counter VHDL description, and more.)

Modelsim简明使用手册，十分适合新手使用-Modelsim concise user manual is very suitable for novice to use

FIFO程序，适用FPGA仿真的代码，有一定的价值-FIFO

说明：  平方环载波同步法FPGA实现的verilog代码(square loop carrier wave syn)

altera官方的各种有用的参考资料，都是自己收集的，遇到问题可以很方便的查看(altera official variety of useful references, are their own collection, problems can easily view)

xilinx ddr3最新VHDL代码,通过调试(xilinx ddr3 latest VHDL code through debugging)

直流电机控制器，属于精品vhdl源码，可在eda仿真工具上仿真实现-DC motor controller is excellent VHDL source code can be sown in simulation tools Simulation