用VHDL语言实现的图像传感器TCD132D的时序驱动代码,时序精准!

CODE_VHDL_INITIALIZING 液晶电视 DISPLAY(KHỞI TẠO HIỂN THỊ LCD)

此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development kit EasyFPGA030.

这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)

VHDL实现简单的8位CPU doc文件上有源代码-VHDL simple eight CPU doc documents Active code

modelsim仿真，大量vhdl程序，验证，很有价值！(The ModelSim Simulation, a large number of VHDL procedures, validation, great value!)

在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表(In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch)

在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.

vhdl对dds的原理设计，由衷要得论文价值。不后悔-right dds VHDL design principle, we sincerely value of fine papers. No regrets

在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector

FPGA设计的四种常用思想与技巧，包括乒乓操作、串并转换、流水线操作、数据接口同步化(FPGA design of the four common ideas and techniques, including the operation of ping-pong, SERDES, pipelining, synchronization of data interface)