这是用VHDL编写的译码程序,程序简单易懂

altera 公司的15IP源码 亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER

基于FPGA的等精度数字频率计，包含FPGA和单片机通信程序，解释非常详细。经过调试成功。(FPGA-based Precision Digital frequency meter, including FPGA and MCU communication program, explained in great detail. After successful commissioning.)

说明：  基于FPGA的QPSK调制解调电路设计与实现 (QPSK)

一个电子秒表，最大显示59.99,具有暂停和reset功能(An electronic stopwatch, the maximum display 59.99, with a pause and reset functions)

串并转换程序，由串行输出转换为4位的并行输出-String and the conversion process, from the serial output is converted to 4-bit parallel output

基于可编程逻辑器件FPGA的独立式键盘设计，内部具有硬件去抖动电路。值得一看-FPGA-based programmable logic device stand-alone keyboard design, the internal hardware to jitter circuit. Worth a visit

ＶＨＤＬ编写的flash控制器源代码.包含testbench。-Prepared by flash controller VHDL source code. Contains testbench.

利用FPGA，产生三相SPWM波，与后继硬件电路配合，形成三相电源。高效，实用。(Using FPGA, produce three-phase SPWM wave, with subsequent hardware circuit with the formation of three-phase power. Efficient and practical.)

A counter that starts from 0 and increments mod 16 on each rising edge of the clock

这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.(This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.)