这是用VHDL编写的译码程序,程序简单易懂

说明：  基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.(Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the button to switch the modulation of 25 , 50 , 75 and short press button to switch the modulation signal frequency 1k, 1.5k, 2k, 2.5k.)

用verilog实现sd卡读写，亲测可用(Implementation of SD card read and write with Verilog)

BUS documentation and map reffereces

saber的仿真模型，是一个电源的，经过调试已经成功(The simulation model of the saber, is a power, after commissioning has been successfully)

xilinx FPGA 与高速ADC LVDS接口的范例程序(xilinx FPGA ADC LVDS interface)

课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL

3x3中值滤波器的FPGA实现现(VERILOG)可直接使用。 (3x3 median filter FPGA implementation of the present (VERILOG) can be used directly.)

verilog编写的全功能串口-verilog programme of serial port

利用FPGA采集按键，加了消斗。其实跟单片机的效果差不多。-The use of FPGA collect keys, plus the elimination fighting. In fact, almost with the effect of SCM.

FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错(FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA)