VHDL实现SPI功能源代码

适用于NIOS II的1024点FFT C算法( 1024-point FFT C algorithm for NIOS II)

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS/2 keyboard interface bus VHDL source code, Based on Xilinx spartan3

四种常用FPGA设计技巧，包括乒乓结构等。-Four kinds of commonly used FPGA design skills, including ping-pong structure.

关于vhdl对硬件接口8237的编程，可以在进行fpga/cpld设计是作为模块用到-VHDL for the hardware interface on the 8237 programming, you can carrying out fpga/cpld design is used as a module

2ask调制与解调的源代码，经过测试可用(2ask modulation and demodulation source code is available, tested)

the 8 bit alu by verilog

fpga的RS485代码,非常容易，适合学习(the code of rs485 in fpga, very easy,suitable for learning)

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation