这是DES的Verilog源代码（数据加密标准）是用来在N.

资源描述针对于Virtex5FPGA的DDR2读写测试的完整工程,已测试可以使用，可以根据自己的ddr2配置自行更改。。。。

Arbiter code for simulation purpose

ofdm系统的matlab实现，包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)

VHDL 2FSK调制解调器各部分的原理与代码(The principle and code of each part of the VHDL 2FSK modem)

AD7685芯片采集程序，可以自行设置采样率，经检验可用。(The AD7685 chip collection procedures, available.)

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

三十个vhdl源码，对于刚开始学习vhdl的很有帮助，可以帮助理解数字电路-30 vhdl source for the beginning of the study vhdl helpful, and can help to understand digital circuit

VHDL描述的时钟分频电路，用途广-VHDL description of the clock divider circuit, uses widely ...

FPGA做VGA通讯的详细资料，我找了很久才收集起的，很有用，可供初学者学习实用-FPGA to do VGA communication details, I am looking for a long time before starting the collection, very useful for beginners to learn practical

verilog coding for butterworth filter with cut off frequency with 500hz