这是DES的Verilog源代码（数据加密标准）是用来在N.

实现了简单的电子表功能，是24小时，用VHDL所编写的，quartus ii 7.2-To achieve a simple spreadsheet functions, is 24 hours, using VHDL prepared, quartus ii 7.2

VHDL版的C8051核(C8051).evatronix公司的IP核-VHDL version of the C8051 core (C8051). Evatronix company s IP core

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE

常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题(Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging)

NAND型闪存接口程序 里面包含了datasheet以及测试程序 (NAND flash memory interface program)

vga 测试代码，可以显示任意彩条，棋盘，花纹(VGA test code, can display any color bar, chess board, decorative pattern )

用VHDL编写的计算器，能实现简单的加减乘除四则运算

说明：  Implementing QPSK using DSS

根据音乐发生的机理，将复杂可编程逻辑器件作为发生音乐的核心器件，用高速集成电路硬件描述语言编程描述发生的音乐乐谱，配合周边硬件电路，由电声转换发声器接收信号，从而发出音乐声，实验表明，采用该方法设计的音乐发生器成本低、修改方便-Music took place in accordance with the mechanism of complex programmable logic device, as occurred in the core of music devices, with high-speed integrated circuit hardware description language to describe the occurrence of music notation, with the peripheral hardware circuits, electro-acoustic conversion by the audible signal device to receive signals, which issued music, experiments show that this method of music generator design and low cost, easy to amend

一个八位的并行输入，串行输出的编码器；带有开头结尾帧。(It is an encode with eight palallel input and a serial output.)