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oled
驱动0.96寸的oled显示数字和字母,(Drive 0.96 inch OLED to display numbers and letters.)
- 2021-01-14 16:28:46下载
- 积分:1
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tcp_ip_core_w_dhcp_latest.tar
以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)
- 2018-08-23 14:35:01下载
- 积分:1
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cpld 控制 8
cpld 控制 8-32M sdram 控制器 maxII epm570实现。-CPLD control 8-32M sdram controller maxII epm570 realize.
- 2022-02-20 19:59:10下载
- 积分:1
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DCM_SP
数字时钟管理器,xilinx公司开发板集成时钟,实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)
- 2021-02-19 09:59:44下载
- 积分:1
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2004 SNUG of systemverilog
2004 SNUG of systemverilog
- 2022-09-09 13:40:02下载
- 积分:1
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APB 总线
APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
- 2017-08-22 16:04:06下载
- 积分:1
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VHDL prepared by the FIR filter source for Embedded designers have a good role i...
VHDL语言编写的FIR滤波器源码
对于嵌入式设计者有很好的指导作用
-VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
- 2022-06-17 20:08:46下载
- 积分:1
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VHDL上机手册(基于Xilinx ISE)
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VHDL上机手册(基于Xilinx ISE)
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1 ISE 软件的运行
2 创建一个新工程
3 创建一个VHDL源文件框架
4 输入VHDL程序
*5 仿真
6 创建Testbench波形源文件
7 设置输入仿真波形
-eda
- 2022-08-03 00:33:41下载
- 积分:1
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译码器,将八位输出转换为七段译码显示,相当于7448驱动译码管...
译码器,将八位输出转换为七段译码显示,相当于7448驱动译码管-Decoder, the 8 output is converted to seven segment decoding shows that the equivalent of 7448
- 2022-05-30 05:04:27下载
- 积分:1
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McBSP
CPLD对mcbsp的收发操作,占用资源很少(CPLD to mcbsp transceiver operation, small footprint)
- 2011-09-14 16:19:51下载
- 积分:1