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fpga0023202323
FPGA时序分析说明。对于高速时钟设计中的时序分析与约束有帮助(FPGA,TIME)
- 2010-11-01 15:49:34下载
- 积分:1
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Fun little FPGA that plays a portion of Habanera
Fun little FPGA that plays a portion of Habanera
- 2022-03-20 13:10:02下载
- 积分:1
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这是我的毕业设计的SVPWM使永磁交流同步电动机…
这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统,里面除了一个SVPWM的驱动算法之外,还有一个步进电机的控制器,以及基于QUARTUS7.2的NIOS II控制核心,通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂,运用的知识也比较多,在SVPWM算法,PID算法,步进电机控制方面,NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译,目标芯片是选用EP1C6Q240-This is my graduation project SVPWM make a permanent magnet AC synchronous motor control system, which apart from a driver SVPWM algorithm, there is a stepper motor controller, as well as QUARTUS7.2 based on the NIOS II control core, through PC serial port can be controlled permanent magnet AC synchronous motor and stepper motor for accurate positioning. The system is more complicated, the use of more knowledge, in the SVPWM algorithm, PID algorithm, stepper motor control, NIOS II serial programming, such as places are worth considering. QUARTUS7.2 compile the best use of the target chip is optional EP1C6Q240
- 2023-05-08 19:40:04下载
- 积分:1
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曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取...
曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取出来作为同步信号,使接收端的时钟与发送设备的时钟保持一致-Manchester coding techniques that use voltage changes in 0 and 1. Provisions in the middle of each symbol hopping happen. High → low hopping express 0, low → high jump for the express one. Symbol between each transition must happen, this change in the receiver can be extracted as a synchronization signal to the receiving end of the clock and send the equipment to maintain the same clock
- 2023-06-17 15:30:03下载
- 积分:1
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sdram_module3
能够实现16位的SDRAM的读写,没有仿真文件,只有SDRAM读写的源代码,用Verilog编写(can complete read or write sdram, only include Verilog code and no simulation files)
- 2013-11-25 12:43:11下载
- 积分:1
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基本逻辑门电路的设计方法,或门的VHDL的设计让你更容易步入VHDL的设计氛围中,简单的或门编制...
基本逻辑门电路的设计方法,或门的VHDL的设计让你更容易步入VHDL的设计氛围中,简单的或门编制-Basic logic gate circuit design methods, or the door of the VHDL design allows you to more easily into the VHDL design environment, the simple OR gate preparation
- 2022-01-30 19:12:35下载
- 积分:1
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sram_saa1117verilog
图像采集、存储控制verilog源代码,fpga控制SAA1117,采集数据存储到sram,仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)
- 2020-07-09 21:58:55下载
- 积分:1
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zobrazenie_16_bit_cisla_paralel
16 bit switch input view in hexa format on 7seg display
- 2013-08-16 00:50:49下载
- 积分:1
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Escalimetro
all funtions for a scale meter for maps in a 8051 microcontroler with an alphanumeric lcd display
- 2012-12-25 02:14:17下载
- 积分:1
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温度码到二进制吗的转换的verilogHDL代码。
温度码到二进制吗的转换的verilogHDL代码。-Temperature code to do the conversion of binary code verilogHDL.
- 2022-02-28 22:15:49下载
- 积分:1