FPGA to do VGA communication details, I am looking for a long time before starti...

HDL example source code 1/5 dff_as

VHDL implementation using mouse and monitor

FPGA通过AXI总线传输数据给ARM,ARM使用DMA方式接收数据！(FPGA to ARM Bridge design example)

Led灯控制实验用例 目录文件结构： led_test ├─ main.c C语言主源文件 └─ led.c Led灯控制函数源文件(Led lamp control experiment directory file structure use case: led_test ├ ─ main.c C language source file owners └ ─ led.c Led lamp control function source file)

verilog语法说明，包含verilog golden reference guide，verilog 2001语法(verilog golden reference guide)

一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典-Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!

PLL 锁相环verilog程序 可以直接使用(The PLL can be used directly good use)

这个是永磁无刷直流电机的本体结构和控制电路的联合仿真，既可以设计电机的结构，又可以搭电机的控制系统。(This is the body structure of the permanent magnet brushless DC motor and control circuit co-simulation, both the structure of the motor can be designed, they can take control of the motor system.)

60进制减法 相比较 代码效率高 可以进行级联-60 compared to 229 subtraction efficient code can be concatenated

本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段 时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的 大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细 描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity