FPGA控制AG9226代码

fsk调制与解调，此程序经过验证，可以运用，通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use

基于VHDL的多路抢答器，用LCD12864进行显示(Multiplex answering device based on VHDL is displayed with LCD12864)

利用FPGA实现QPSK数字调制。编程采用Verilog HDL语言。(By using the FPGA realization of QPSK digital modulation. Use Verilog HDL language programming. )

本人初学VHDL时编的比较系统的VHDL源程序 巨实用 (I am learning more systematic series of practical VHDL source Giant)

包括Cyclone II EP2C20 原理图.CycloneII开发板原理图fpga.EP1C3T144 FPGA develop board manual.EP1C6Q240C6开发板原理图.EP2C8开发板原理图.EPM1270F256C5 MAX_II_board_schematics.SF-EP1V2+FPGA开发板原理图.XC3S400红色飓风开发板原理图.红色飓风II代开发板原理图2.(Including the Cyclone II EP2C20 schematic . CycloneII development board schematics fpga.EP1C3T144FPGA develop board manual.EP1C6Q240C6 development board schematic . EP2C8development board schematics . EPM1270F256C5MAX_II_board_schematics.SF-EP1V2+FPGA development board schematic . XC3S400red hurricane development board schematics. Red hurricane II development board schematic diagram2)

说明：  stepper motor module on spartan 6 and 24MHz clock fequency

SPI串行总线接口的Verilog实现，详细讲解实现过程。-SPI serial bus interface Verilog realization elaborate on the realization of the process.

实现输入一正弦波和噪声的叠加，介绍详细欢迎下载(The input of a superposition of sine wave and noise introduced in detail)

微分器：利用数字锁相环进行位同步信号提取的关键模块(Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules)

说明：  具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)