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利用fpga实现的DDS,可输出正弦波,输出频率可调
利用fpga实现的DDS,可输出正弦波,输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
- 2022-01-28 18:28:31下载
- 积分:1
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MusicPlayer
说明: 精美的音乐播放器,能加入歌词,和调整歌词显示的快慢。(music player)
- 2011-04-05 19:19:06下载
- 积分:1
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对NC Verilog的基本介绍,详细的图解,非常适合初学者使用,一个word文档和一个pdf文档...
对NC Verilog的基本介绍,详细的图解,非常适合初学者使用,一个word文档和一个pdf文档-NC Verilog on the basic introduction, detailed diagrams, very suitable for beginners to use, a word document and a pdf document
- 2022-08-12 19:52:59下载
- 积分:1
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dowload from : www.fpga.com.cn
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn--- Moore State Machine with explicit state encoding-- dowload from : www.fpga.com.cn
- 2022-04-23 20:22:54下载
- 积分:1
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vhdl的3
vhdl的3-8译码器-instantiate the 3-8 decoder
- 2022-03-25 00:36:10下载
- 积分:1
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Using Verilog to write a serial transmission to the parallel transmission of the...
一个用verilog写的串行传输到并行传输的程序,在quaters下编的-Using Verilog to write a serial transmission to the parallel transmission of the procedure, under the quaters
- 2022-06-14 12:50:53下载
- 积分:1
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or2a
使用vhdl语言设计一位全加器,在仪器上下载并实现LED灯的闪亮(A full adder design)
- 2013-09-26 18:24:15下载
- 积分:1
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VHDL
带有异步清零、异步置位功能的边沿JK触发器(With asynchronous reset, asynchronous setting function of edge JK flip-flop)
- 2020-06-30 03:00:02下载
- 积分:1
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用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。...
用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
- 2022-10-05 02:20:03下载
- 积分:1
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VHDLshuzidianlushejijiaocheng
VHDL数字电路设计教程
乔庐峰等译 当当网销量领先(VHDL tutorial on digital circuit design: (Brazil) Pedroni (Pedroni, VA) were, Joe Lu Feng, M. Publisher: Electronic Industry Press Dangdang sales leader)
- 2010-08-07 10:37:05下载
- 积分:1