vhdl的3

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on

关于i2c master/slaver control 方面的技术资料 介绍其特色与使用方法(On the i2c master/slaver control of technical information on their characteristics and use)

rs255编码解码器，verilog描述，FPGA实现(RS255 223 ENCODER)

ASK,FSK,PSK,DPSK调制解调的详细仿真代码(ASK, FSK, PSK, DPSK modulation and demodulation detailed simulation code)

This file contains async fifo design

说明：  Verilog代码实现四分屏，在Vivado平台下实现的，可仿真(Verilog code realizes four screens, which can be simulated under vivado platform)

VHDL_count 从 0 到 9 4 7 段 LED 显示 4 脉冲使 （đếm 慈 0 đến 9 hiển 施耐 4 带领 7 đoạn với 4 xung 启用）

基于状态机的优秀SPI输出程序（以DAC7512为基础，可修改）(VHDL code about SPI)

数字钟，数字电子技术课程设计常用内容，基于basys3平台(Digital clock, digital electronic technology curriculum design commonly used, based on the basys3 platform)

说明：  编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法(Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange)