murata ads 2011 model

说明：  将外部的输入的6Mhz的信号分成为频率为153600hz的信号(The external input signal divided into 6Mhz 153600hz signal frequency)

分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.

说明：  Verilog简易教程，或者说是讲义，清晰易懂，适合初学者入门使用(Layman' s Guide to Verilog, or a lecture, legible entry to use for beginners)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

vhdl的基础性的介绍，对初学者大有用处-vhdl basic introduction

设计了一个电子时钟，功能包括定点报时，设置闹钟，校时等(Designed an electronic clock, features include fixed-point timekeeping, setting alarms, school hours, etc.)

用于检测信号上升沿，输出与时钟相关的正脉冲(Detect the rising edge of the signal)

这是我的VHDL格式的电子密码锁源程序，请站长审核啊-This is my VHDL source code format of the electronic lock, please review ah owners

FPGA功耗分析工具EPE用于分析FPGA系统的功耗(FPGA power analysis tools EPE is used to analyze the power consumption of the FPGA system)

TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus