alter FPGA，包含sdram的nios系统开发实验完整工程文件

System Verilog decodificator. Enters a value(binary), drops hundreds, tens and units in BCD

E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)vhdl

ALTERA FPGA CLPD

这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.

多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd-Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd

APB总线协议转I2C总线协议的接口IP，verilog代码实现，包含详细testbench(APB bus interface to I2C bus interface IP，verilog code )

floating point divider

用fpga实现SDI（ xapp1014-xilinx-sdi）赛灵思原厂资料(Using fpga implementation SDI (xapp1014-xilinx-sdi) Xilinx original data)

利用matlab，对偏振控制器进行仿真，最终在邦加球上进行显示(Using matlab, simulation of the polarization controller eventually be displayed on the Poincare Sphere)

说明：  载波同步是QPSK信号相干解调的一项关键技术。(Carrier synchronization signal coherent QPSK demodulation is a key technology.)