8085汇编实现计算器

该工程文件实现ARM系统中CPLD的逻辑工作，起到外围资源的逻辑地址译码功能-realization of the project document ARM system CPLD logic, external resources have address decoding logic function

FPGA中嵌入8051的核 并且实现控制128*64的液晶显示-FPGA embedded in 8051 and to achieve control of the nuclear 128* 64 LCD

用VERILOG实现一个被除数为8位、除数为4位的高效除法器(With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider)

bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

ahb总线Verilog代码及Verilog仿真文件(ahb bus Verilog code and Verilog simulation code)

block-LDPC 译码VHDL 源代码(block-LDPC decode VHDL source)

VHDL_count 从 0 到 9 4 7 段 LED 显示 4 脉冲使 （đếm 慈 0 đến 9 hiển 施耐 4 带领 7 đoạn với 4 xung 启用）

4*4键盘小程序 两种算法内附检查LED(4* 4 keyboard applet containing two algorithms check the LED)

full adder in vhdl of 4 bits

每次开机都将次数加1 并存储到EEPROM。这样就能直观的看到机器的使用次数 用P1口 LED做为显示，次数大于256是将溢出，按复位模拟开机 或者直接通过开关开机(Each boot will add a number of times and stored to the EEPROM. So you can visually see the frequency of use of the machine as with P1 port LED display, the number is greater than 256 will overflow, analog power or press the reset switch power directly through)