8085汇编实现计算器

代码风格非常好，容易看懂，移植性高

When the initial input falls between the Switch off point and Switch on point values, the initial output is the value when the relay is off.

TLC5510的驱动程序，采用Verilog语言编写(TLC5510 driver, the use of Verilog language)

这是使用systemgenerator的一个入门程序和范例使用matlab和system generator共同实现，并配有教学文档，清晰简单，易懂(This is an entry using systemgenerator procedures and examples using matlab and the system generator together to achieve, and with a teaching document, clear and simple and easy to understand)

说明：  DDS的基本原理主要由五部分组成，分别是；相位累加器，正弦波形存储器，数模转换器，低通滤波器和时钟，将相位累加器输出的数据作为地址，用来查询表的数据，将取出的正弦数据通过数模转换器输出模拟信号，模拟信号再通过一个低通滤波器输出纯净的正弦波信号。(The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal.)

说明：  Verilog实现的加减法功能计数器，通过独立的自增自减信号控制计数器进行自增计数和自减计数(Function counter of addition and subtraction implemented by Verilog)

这是二十四进制计数器的源程序，有需要的同学可以参照一下！(This is 24 hexadecimal counter source, needy students can refer to you!)

说明：  假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)

vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural