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一个有效的高吞吐量的FPGA的AES实现多千兆位协议
应用背景在本文中,我们提出了一种高效的非流水线式AES-128实现高实施吞吐量,以便它可以使用在千兆协议。我们实现我们的AES-128加密设计在Xilinx Virtex-7 FPGA解密了4.86 Gbps的5.30/ ECB模式和5.23/4.84吞吐量在CBC模式Gbps。关键技术由于高吞吐量的要求加密信道的体系结构,一种高效的实施硬件是必要的。这可以实现通过使用高端可重构智能利用平台。实现令人信服的高吞吐量,一高效的非流水线式的先进实现数据加密标准(AES)和密钥长度为128比特,用于千兆位现场可编程门阵列(FPGA)协议提出。
- 2022-11-26 08:05:03下载
- 积分:1
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uart
通过串口发送,实现FPGA与stm32的dds发生器(Implementation of DDS generator)
- 2018-11-28 09:19:29下载
- 积分:1
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8-fft
FFT 8 PT RDX 2 USING VERILOG
- 2014-03-31 02:35:31下载
- 积分:1
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vivek
THIS IS A SOURCE CODE FOR LIFT IN VHDL LANGUAGE
- 2012-04-08 02:01:07下载
- 积分:1
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LED和MAX II开发epm1270f256c5测试按钮
应用背景****************************************************************************关键技术这个项目的目的是研究开发板的最大。该项目是实现闪烁的发光二极管具有不同的频率和/关闭时,你按按钮。
- 2023-04-18 06:05:03下载
- 积分:1
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基于DDS的移相信号发生器的设计
4、各个功能的主要源程序
1、移相模块:
= 1 * GB2 * MERGEFORMAT ⑴、相位累加器:
architecture one of add32 is
begin
s
- 2023-02-10 04:25:04下载
- 积分:1
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altera嵌入式设计大赛文章,车载cots设计实现
altera嵌入式设计大赛文章,车载cots设计实现-Embedded Design Contest altera article, cots Car Design
- 2022-05-20 14:21:28下载
- 积分:1
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PCPU设计代码
说明: RISC 5级流水线CPU,带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)
- 2020-06-24 04:00:01下载
- 积分:1
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gamefive
高精度小数除法器设计与实现。
在FPGA开发板上实现小数除法器,输入输出信号N_in [15:0], D_in[15:0],N_in[15:0]小于D_in,即被除数小于除数,输出商Q_out[15:0]中Q[15]一定为0,Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)
- 2017-01-01 17:32:25下载
- 积分:1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分:1