基于VHDL的点阵控制

此代码可以实现16位二进制和BCD码之间的转换。(This code can realize the conversion between 16 bit binary and BCD code.)

说明：  how to come ture a costas loop in FPGA with verilog,it is very useful on project

华为内部资料，华为FPGA全套资料，包括华为的专利设计(Internal information Huawei Huawei FPGA complete information, including Huawei' s patented design)

A multiplier unit in VHDL

mc8051代码，里面功能齐全，调试方便(mc8051 code, inside a full-featured, easy debugging)

canbus verilog实现，原代码文件-canbus verilog implementation, the original source document

An odd parity checker as an FSM using VHDL

基于BCH码的ECC纠错算法，可纠错2位错误码，供参考(Based on BCH code ECC error correction algorithm, two error codes can be corrected for reference.)

OFDM modulation source code written in Matlab

利用VHDL语言描述出一个双脉冲，可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)