Verilog code for RS

基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design

说明：  基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)

倍频器-WE

这个程序为通信中的16QAM调制程序，可用于无线或有线通信系统的调制仿真之用。(The 16QAM modulation communication this program can be used for wireless or wired communication system modulation simulation purposes.)

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)

Verilog编写的简单异步串口 完全原创，站长请查看内容-Verilog prepared by the simple asynchronous serial completely original, the station can be accessed content

多相抽取滤波器。分四相，两倍抽取，采用16阶FIR滤波器实现(Polyphase decimation filters. Divided into four phases, extracted twice using 16-order FIR filter implementation)

useful VHDL document for programmer

fpga永磁同步电机矢量控制系统，包括死区等模块(fpga foc)