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lanqiu24s8
篮球24s计时。计时器递减计数到零时,数码显示器显示‘0’并停止,同时发出报警信号(basketball 24 seconds)
- 2012-06-11 16:04:01下载
- 积分:1
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c4gx_f896_host_ddr2a_odt
ALTERA PCIE FPGA开发板(EP4C平台)DDR2内存测试代码(ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code)
- 2011-09-07 11:57:21下载
- 积分:1
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PS2_KB11
键盘计算器,可实现加减乘数运算
基于fpga nios2(Keyboard, calculator, addition and subtraction can be realized based on fpga nios2 multiplier operator)
- 2011-05-19 10:28:42下载
- 积分:1
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《CPLDFPGA verilog DA0832调控
verilog da0832 cpldfpga control-verilog da0832 cpldfpga control
- 2022-12-07 05:55:03下载
- 积分:1
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速率发生器
应用背景通用模块,以产生可重构的源时钟频率的传输速率。该模块可用于UART,自定义串口协议等。提供一个时钟发生器模块产生可选 ;-波特利率和;——时钟源(可选择分因素) ;还产生接收 ;——时钟的16倍,8倍,倍,倍的传输波特率 ;关键技术UART,VHDL,FPGA,CPLD programmanle逻辑器件。设备无关的代码
- 2023-01-24 03:05:04下载
- 积分:1
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RS_255_223_ENCODER
rs255编码解码器,verilog描述,FPGA实现(RS255 223 ENCODER)
- 2015-03-30 09:52:09下载
- 积分:1
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airthmatic & logic unit
airthmatic & logic unit
- 2023-02-23 08:10:03下载
- 积分:1
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基于任意波形发生器的实现可编程逻辑器件…
基于可编程逻辑器件实现任意波形发生器VHDL源代码-Programmable logic device based on the arbitrary waveform generator implementation VHDL source code
- 2023-05-09 22:45:03下载
- 积分:1
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IIR
利用dsp builder设计的IIR滤波器,已经验证完全可以使用,只需要把其中系数改变。内含VHDL代码(Design IIR filters by dsp builder have been verified , just change the coffetions including VHDL code.)
- 2020-12-02 19:59:26下载
- 积分:1
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Routine application of this experiment in the Actel Flash architecture ProASIC3/...
此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA,适合于FPGA及Verilog HDL的初学者,配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development kit EasyFPGA030.
- 2022-05-14 23:14:31下载
- 积分:1