bist coding

数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through the target chips EPF10KLC84-4 verification

说明：  16级流水线型cordic旋转代码以及测试文件，亲测好用(16-stage pipelined cordic rotation code and test files, pro-testing)

说明：  Arty Z7 20 HDMI output

设计一个可编程间隔定时器，完成8253的功能，实现以下几点要求： 1、 含有3个独立的16位计数器，能够进行3个16位的独立计数。 2、 每一种计数器具有六种工作模式。 3、 能进行二进制/十进制减法计数。 4、 可作定时器或计数器。 -The design of a programmable interval timer, 8253 to complete the function, realize the following requirements: 1, contains three independent 16-bit counter, capable of three independent 16-bit count. 2, each with six counter mode. 3, can be binary/decimal subtraction count. 4, can be used for the timer or counter.

基于FPGA器件的DDS设计实现中的一个核心部分就是波形存储表的设计。首先采用LPM_ROM和 VHDL选择语句这两种方法进行波形存储表的设计和比较分析 然后考虑到硬件资源的有限性及DDS的精度要 求,对这两种方法的程序进行了优化 最后对这两种方法设计的程序进行仿真和硬件调试。结果表明:采用这两种 方法都能有效地实现DDS中波形存储表的设计。 (DDS-based FPGA devices designed to achieve one of the core of the waveform is stored in table design. First of all, choose to adopt LPM_ROM and VHDL statements of these two methods for the design waveform storage tables and comparative analysis and then, taking into account the limited hardware resources and the accuracy of DDS, the two methods to optimize the process the last of these two methods of process design simulation and hardware debugging. The results showed that: the use of these two methods are all effective ways to achieve the DDS waveform stored in the table design.)

流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))

附件 介绍了如何 使用compxlib命令编译Xilinx的ModelSim仿真库，创建这个仿真库对ISE调用modelsim是必不可少的一步,该法完全自动化，免去繁杂的手动操作，是创建这个仿真库最简洁的方法之一-Annex compxlib introduce how to use Xilinx

内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用(Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly)

说明：  在quartus下搭建的数字锁相环，能实现频率自动跟踪。(The digital phase-locked loop built under quartus can realize automatic frequency tracking.)

用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver