bist coding

将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)

io 组件，用vhdl实现io端口的控制，包括输入输出，握手信号，-io port VHDL code

讲述4ASK的原理并附有matlab调制解调的源码。。。。。。。。。。 注：原来上传的4ASKmod.zip不要下(The principle tells 4ASK together with modulation and demodulation matlab source. . . . . . . . . . Note: The original upload 4ASKmod.zip not down)

verilog lcd2864 适合初学者(verilog lcd2864 )

FPGA编写的三角波发生器，可以产生100HZ～500KHZ以上的三角波，波形稳定(FPGA prepared triangular wave generator, can produce more than 100HZ ~ 500KHZ triangle wave, waveform stability)

利用VHDL实现CPLD（EMP240T100C5）的PWM输出-Using VHDL realize CPLD (EMP240T100C5) of the PWM output

利用fpga实现的DDS，可输出正弦波，输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable

turbo product code used in error correction

说明：  可调矩阵，最大32*32位浮点数乘法矩阵及仿真。(32*32 floating multiplication matrix)

FPGA板上的锁存器PLL控制代码（verilog代码）(FPGA board latch the PLL control code (Verilog code))