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hdb3_v3
Quartus环境下使用Verilog编写的HDB3编解码程序,RTL和时序仿真已过(Quartus under the environment of a HDB3 protocol procedures written in Verilog, RTL and timing simulation has be passed)
- 2015-11-24 21:56:05下载
- 积分:1
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VHDL_Snake_Game
在FPGA开发板上用VHDL语言实现了贪吃蛇游戏,开发软件为quartus 2.这是详细的实验报告,包括源码(Snake game with VHDL FPGA development board, software development quartus 2 This is a detailed experimental report, including the source)
- 2012-06-25 16:15:26下载
- 积分:1
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20753
基于VHDL的FPGA开发快速入门·技巧·实例 ,电子工程师创新设计必备宝典系列之FPGA开发全攻,未来,FPGA 开
发能力对工程师而言将成为类似C 语言的基础能力之一,面对这样的发展趋势,你还能简单地将FPGA 当成一种逻辑器件吗?还能对FPGA 的发展无动于衷吗?(基于VHDL的FPGA开发快速入门·技巧·实例 )
- 2013-12-19 09:33:31下载
- 积分:1
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sobel-with-verilog-language
用verilog实现sobel边缘检测算法(sobel edge detection with verilog language)
- 2020-07-12 19:38:53下载
- 积分:1
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modulation-and-demodulation
调制与解调系统的FPGA设计实现,包括2-ASK调制和解调,2-FSK调制和解调,2-PSK调制和解调,QPSK调制和解调,PPM调制和解调的verilog源代码。(FPGA design implementation of modulation and demodulation system, including 2-ASK modulation and demodulation, 2-FSK modulation and demodulation, 2-PSK modulation and demodulation, QPSK modulation and demodulation, PPM modulation and demodulation verilog source code .)
- 2021-04-09 09:29:01下载
- 积分:1
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接口键盘和液晶屏上AT89S52代码
接口键盘和液晶屏上AT89S52代码
- 2022-04-22 04:25:15下载
- 积分:1
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AD9250 204b Verilog源码
说明: AD9250是一款双通道14位ADC,最高采样速率250 MSPS,JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)
- 2021-04-14 11:01:55下载
- 积分:1
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SYSTEMVIEWQPSK
使用 System view 编程 QPSK(use System Programming view QPSK)
- 2021-01-04 21:38:54下载
- 积分:1
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apb.v
AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
- 2021-04-17 20:38:53下载
- 积分:1
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cla - Copy
说明: ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER
- 2019-03-19 01:35:37下载
- 积分:1