altera 公司的15IP源码 亲自测试还不错 有DIV, CONTER

tdma参数化模块。可以自动生成2的n次的tdma哥时隙，用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)

自己编写的C++的类的测试程序，有详细的注注释，对初学者有很大帮助！！！(The own written C++ class test program, detailed annotation of Note of great help for beginners! ! !)

用verilog编程的TCON模块（时序控制器）的程序(Verilog programming module with TCON (timing controller) program)

应用背景FPGA原型的VHDL例子提供一系列清晰，易于遵循的快速代码开发模板；大量的实际例子来说明和强化的概念和设计技术；现实可实施的项目和测试在Xilinx原型板；深入探索和Xilinx PicoBlaze软核微处理器。关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。

EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)

des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language

用fpga实现SDI（ xapp1014-xilinx-sdi）赛灵思原厂资料(Using fpga implementation SDI (xapp1014-xilinx-sdi) Xilinx original data)

Z源逆变器简单升压模拟仿真。调制方式为SPWM，通过设置三角波幅值和比较电压，即可调节输出电压。(Z-source inverter simple step-up simulation. Modulation mode SPWM, by setting the the triangle amplitude and the comparison voltage to regulate the output voltage.)

ac97 VHDL core

用FPGA实现的VGA接口程序，采用的语言是VHDL硬件描述语言，大家可以参照下看看采用的器件是Altera EP2c35-Using FPGA to achieve the VGA interface program, the language used is VHDL hardware description language, we can see under the light of the devices used are Altera EP2c35