基于VHDL的多功能调制解调器设计

数字电子钟设计完整设计，包括原理介绍，程序设计，波形仿真-Design a complete digital electronic clock design, including the principle of introduction, program design, waveform simulation

原理图输入法制作的32位加法器。。。。。。。。(adder32)

自动售货机，投币自动售货 MaxplusII下运行-Vending machines, coin-operated automatic vending MaxplusII run

说明：  利用vhdl语言编写的译码器程序，采用两种不同方式(The use of language decoder vhdl program, using two different ways)

fpga平台实现srio通信，以及srio端口寄存器设计。(FPGA platform to achieve sRIO communication, as well as sRIO port register design.)

verilog，FPGA的TDC电路设计(verilog ，TDC base on FPGA)

说明：  资料的内容是实现旋转机械同步整周期采样的数据采集系统相关文献资料，包括鉴相信号如何倍频，机械振动信号相位如何检测等的实现方法。(Information content is for rotating mechanical synchronization synchronous sampling data acquisition system-related documents, including the Kam-believe number to harmonic mechanical vibration signal phase to detection of realization.)

verilog入门基础以及简单编程介绍，verilog是近几年发展迅速的一门硬件语言-Verilog entry basis, as well as introduce a simple programming, verilog in recent years the rapid development of a hardware language

这是执行高速的代码通用异步收发器代码是用VHDL写的语言.UART是一种在传输端进行并行输入和串行输出，在接收端进行串行输入和并行输出的算法。

数字频率计VHDL程序与仿真 文件名：plj.vhd。 --功能：频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的 --高4位进行动态显示。小数点表示是千位，即KHz。 -Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.- Function: frequency meter. With four shows that will automatically count seven decimal results, automatic selection of effective data- four for the high dynamic display. Decimal point that is 1000, or KHz.